`timescale 1 ns / 1 ps
/*------------------- include --------------------*/

/*---------------------------------------------*/

`define CLOCK_FREQ_MHz 12.0   //系统主频 MHz
`define BSP  115200 

`define BSP_DALAY #(1000000000/`BSP)

`include "top.v"

module tb; 

reg clk ; 

reg rst_n;          //复位信号
reg [7:0] isr ;

//生成时钟
parameter NCLK = 1000/`CLOCK_FREQ_MHz; 
initial begin
	clk=0;
	forever clk=#(NCLK/2) ~clk; 
end 

initial begin
    $dumpfile("wave.vcd");
    $dumpvars(0, tb);   //dumpvars(深度, 实例化模块1，实例化模块2，.....)
end


initial begin
	isr=8'h55;
	forever begin
        isr = #(NCLK*200) ~isr;
    end
end 


/*----------------------------- 模块 ------------------------------*/
reg rx ; 
top u_top(
    .clk( clk ),
    .rx( rx)
);


task SendData(input [7:0] dat) ;
integer i ; 
begin 
    rx = 1 ; `BSP_DALAY  ;
    rx = 0 ; `BSP_DALAY  ;
    for(i=0;i<8;i=i+1) begin
        rx = dat[i];`BSP_DALAY  ;
    end
    rx = 1 ; `BSP_DALAY  ;
    rx = 1 ; `BSP_DALAY  ;
end
endtask 

task update_rom(input [11:0] addr , input [17:0] dat) ;
begin
    SendData(8'h00) ;
    SendData({4'h0,addr[11:8] }) ;
    SendData(addr[7:0] ) ;
    SendData({ 6'h0, dat[17:16]} ) ;
    SendData(dat[15:8] ) ;
    SendData(dat[7:0]) ;
    SendData(8'hff) ;
end
endtask

task psm_run;
integer i; 
begin
    for(i=0;i<8;i=i+1) begin
        SendData(8'hfe);
    end
    for(i=0;i<8;i=i+1) begin
        SendData(8'hff);
    end
end
endtask 

initial begin
    $display(" -------- psm6 sim ----------");
    rst_n = 0;
    repeat(2) @(posedge clk) ;
    rst_n = 1 ; 
    repeat(2) @(posedge clk) ;
    // SendData(8'h00) ;
    // SendData(8'h51) ;
    // SendData(8'h56) ;
    // update_rom(12'h00 , 18'h01) ;
    // psm_run();
    
    // #(100000000);
    repeat(5000) @(posedge clk) ;

    $display("%d ns:done",$time);
	$dumpflush;
	$finish;
	$stop;	
end

endmodule
